Microprocessor lab exam and interview mcq

Microprocessor lab exam or interview mcq:

1.`BCD code is
 a.a binary code
 b.unsigned code
 c.the same thing as binary numbers
 d.the same as Gray code
answer: (a)
2. the process of fetching and executing instructions,one at a time,in the order increasing addresses is known as
a.instruction execution
b.straight line sequencing
c.instruction fetch
d.random sequencing
(b)
3.the control signal used to distinguish between an I/O operation and memory operation is
a.ALE
b.IO/M'
c.SID
d.SOD
answer:(b)
4.the instruction register holds
a.flag conditions
b.instruction address
c.opcodes
d.none of these
answer:(c)
5.the number of programmable 8-bit registers of 8085 microprocessor is
a.5
b.6
c.7
d.8
answer:(c)
6. the number of register pairs of 8085 microprocessor are
a.3
b.4
c.2
d.5
answer:(a)
7.a microprocessor is said to be a bit, 16 bit etc.depending on its
a.data bus
b.address bus
c.ALU
d.control bus
answre:(c)
8.The instruction register holds
a.flag condition
b.opcode
c.instruction address
d.hex code
answer:(b)
9.the stack and the stack pointer
a. both reside in memory
b.both reside in the CPU
c.former resides in memory but the latter in the CPU
d.former resides in CPU but the latter chip in the memory.
answer:(c)
10.the control signal used to distinguish between an I/O operation and memory operation is
a.ALE
b.IO/M
c.SID
d.SOD
answer:(b)
11.AN 8K*8 ROM , holding the monitor program in a microprocessor trainer kit has the end address.
a.8000H
b.4000H
c.1 FFF H
d.3 FFF H
answer:(c)
12.The total I/O space available in 8085 if used peripheral mapped I/O
a.64
b.128
c.256
d.512
answer:(c)
13.the interfacing device used with an output port is
a.buffer
b. priority encoder
c.latch
d.none of these
answer:(a)
14.address lines require for 64 k_ byte memory chip is
a.13
b.14
c.15
d.16
answer:(d)
15.which of the following is hardware interrupt?
a.INTA
b.TRAP
c.RSTn
d.INT
answer:(b)
16.In 8085 MICROPROCESSOR,which of the following is non-maskable interrupt?
a. RST 7.5
b. TRAP
c. HOLD
d.INTR
answer:(b)
17.RST 7.5 interrupt is
a. vectored & maskable
b. vectored & non-maskable
c.direct & maskable
d. vector and non-maskable
answer:(c)
18.machine cycles in "CALL" instruction of 8085 CPU are
a.6
b.5
c.4
d.3
answer :(b)
19.RST 7.5 interrupt is
a,vectored and maskable
b.non-vectored and maskable
c.non-vectored and non-maskable
d.vector and non-maskable
answer:(a)
20.Machine cycles in "CALL" instruction of 8085 CPU are
a.6
b.5
c.4
d.3
answer:(b)
21.how many hardware interrupt requests a single interrupt controller IC8259A can process?
a.8
b.15
c.16
d.64
answer:(a)
22.the interrupt masks in 8085 can set or reset by the instruction
a.EI
b.DI
c.RIM
d.SIM
answer:(d)
23.the vector address corresponding to software interrupt command RST7 in 8085 microprocessor is
a.0017 H
b.0027 H
c.0038 H
d.0700 H
answer :(c)
24.if clock frequency is 2MHz then the time required for execution of instruction STA 1900H is
a.6.5 millisec
b.13 microsec
c.6.5 microsec
d.10 microsec
answer:(c)
25.in 8085 CPU, the JUMP instruction address affects the
a.accumulator
b.stack pointer
c.H-L PAIR
d.program counter
answer:(d)
26.a single instruction to clear the higher four bits of the accumulator in 8085 microprocessor is
a.XRI 0FH
b.ANI F0H
c.ANI 0FH
d.XRI F0H
answer:(c)
27.machine cycle in "PUSH B" instruction are
a.6
b.5
c.4
d.3
answer:(d)
28.'DAD H' is a
a.data transfer instruction
b.logical instruction
c.I/O & machine control instruction
d. none of these
answer: (d)
29.What will be the content of the accumulator and the status of CY flag after RLC operation, if the content of the accumulator is BC H and CY is 0?
a.79H,1
b.78H,1
c.5EH,0
d.5DH,0
answer:(a)
30.the addressing node used in the instruction STAX B is
a.direct
b.register
c.immediate
d.register indirect
answer:(d)