Half Adder in Digital Logic

Half Adder

A Half Adder is defined as a basic four terminal digital device which adds two binary input bits. It outputs the sum binary bit and a carry binary bit.

Block diagram

Truth Table:

Explanation:

As we have defined above, a half adder is a simple digital circuit used to digitally add two binary bits. A binary bit is either 0 or 1. Hence, there will be four addition combinations these two binary digits and those will be 0+0, 0+1, 1+0 and 1+1.

We know that decimally:

Again, we know that decimal 2 can be represented in two bits binary system as 1 0 (One Zero). Binary two is the smallest double digits number in the binary system. When we add binary 1 with binary 1 we will get both sum and carry since 10 is two digits binary number. When we add 0 to 0, 0 to 1, 1 to 0, we get the sum 0 and 1 respectively and both of them are one digit binary number. Hence, in these  three cases there will be no carry during addition or carry is 0 here. We can summarise this in a truth table for the half adder.

Half Adder Truth Table:

From the above truth table, we can see that the sum digit of two binary inputs is the outcome of XOR operation and we can realize it by using an XOR gate.

Carry digit of those two binary inputs is the outcome of AND operation and we can realize it by an AND gate.

Half-Adder logical circuit:

So, the Half Adder is designed by combining the 'XOR' and 'AND' gates and provide the sum and carry.

There is the following Boolean expression of Half Adder circuit:

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on "Half Adder"

1. In parts of the processor, adders are used to calculate ___________

A) Addresses
B) Table indices
C) Increment and decrement operators
D) All of the Mentioned

View Answer = (D) All of the Mentioned
Explanation:- Adders are used to perform the operation of addition. Thus, in parts of the processor, adders are used to calculate addresses, table indicess, increment and decrement operators, and similar operations.

2. Half-adders have a major limitation in that they cannot _________

A) Accept a carry bit from a present stage
B) Accept a carry bit from a next stage
C) Accept a carry bit from a previous stage
D) Accept a carry bit from the following stages

View Answer = (c) Accept a carry bit from a previous stage
Explanation:- Half-adders have a major limitation in that they cannot accept a carry bit from a previous stage, meaning that they cannot be chained together to add multi-bit numbers. However, the two output bits of a half-adder can also represent the result A+B=3 as sum and carry both being high.

3. If A and B are the inputs of a half adder, the carry is given by _________

A) A AND B
B) A OR B
C) A XOR B
D) A EX-NOR B

View Answer = (A) A AND B
Explanation:- If A and B are the inputs of a half adder, the carry is given by: A(AND)B, while the sum is given by A XOR B.